Автор: Ashok B. Mehta
Название: SystemVerilog Assertions and Functional Coverage
Издательство: Springer
ISBN : 978-1-4614-7323-7
Год: 2013
Количество страниц: 374
Формат: PDF
Размер: 28 Mb
Язык: English
Для сайта: MirKnig.com

This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage. Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question have we functionally verified everything.

Автор: Ashok B. Mehta
Название: SystemVerilog Assertions and Functional Coverage
Издательство: Springer
ISBN : 978-1-4614-7323-7
Год: 2013
Количество страниц: 374
Формат: PDF
Размер: 28 Mb
Язык: English
Для сайта: MirKnig.com

This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage. Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question have we functionally verified everything.